Extreme Tech announced that the Hybrid Memory Cube Consortium, which consists of such silicon heavyweights as Micron, Samsung, and IBM (but not Intel), finished hammering out the Hybrid Memory Cube (HMC) 1.0 standard this week. With a max bandwidth of 320GB/sec to a nearby CPU or GPU (compared to 24GB/sec for DDR3 SDRAM), HMC offers up to 15 times the performance of DDR3, while using 70% less energy. Rather than placing RAM dies next to each other (as seen with today’s DRAM), the Hybrid Memory Cube design stacks the memory dies connecting them to each other via through-silicon-vias (TSVs) Stacking the dies shortens the wires between them allowing data to be sent at a higher speed while using less energy. The design is similar to smartphone SoCs, where the memory chip is stacked on top of the CPU/GPU, allowing the completed device to be significantly smaller. In addition, HMC removes the logic transistors from each DRAM die and places them all in one central location providing a single logic circuit to drive all memory dies (which offers further improved performance).
HMCs are expected to launch later this year, likely appearing first in supercomputers and networking devices while we wait for Intel to cave in or develop their own copycat technology.