Micron is walking away from one of the semiconductor industry’s most tantalizing DRAM designs. After roughly two decades of research, the company says it will not commercialize future 4F² DRAM, arguing that its theoretical area savings do not translate into a meaningful manufacturing advantage.
The decision came during Micron’s October 21 technology-and-product webinar, led by President and Chief Technology and Products Officer Scott DeBoer. The event was billed as a look at the company’s long-term DRAM, HBM and NAND strategy for the AI era, and Micron’s official investor-relations page confirms the presentation and webcast.
In DRAM terminology, 4F² describes a memory-cell layout occupying four times the square of the minimum feature size, compared with six times that area for the conventional 6F² design. On paper, that is a reduction of about one-third in transistor-cell area, potentially allowing substantially more cells to fit on a wafer. The catch is that the transistor is only one part of the cell: every bit still needs a capacitor, and the capacitor’s dimensions and spacing can dominate the final density.
That physical constraint is at the center of Micron’s argument. DeBoer said capacitor pitch—not the transistor layout’s nominal 4F² or 6F² label—is what ultimately controls bit density. Shrinking the transistor beneath the capacitor therefore does not automatically shrink the complete memory cell. Micron also says 4F² requires added process complexity and expense, undermining the cost-per-bit improvement that made the architecture attractive in the first place. Independent coverage likewise describes the company’s conclusion as a rejection of 4F²’s density advantage on cost and scaling grounds.
Micron’s stance puts it on a different path from Samsung Electronics and SK hynix, which have continued to include 4F²-related structures in their reported technology roadmaps. That does not make Micron’s decision a declaration that the design is impossible; rather, it reflects a judgment that the practical gains are too small to justify the manufacturing burden at the leading edge.
Instead, Micron plans to extract more life from conventional planar scaling while developing future three-dimensional DRAM. The company’s broader roadmap includes continued work across advanced DRAM generations, HBM and AI-focused memory products, with 3D integration positioned as a longer-term answer once cost, yield and performance make the transition worthwhile. Coverage of the webinar says Micron expects additional planar generations before 3D DRAM becomes ready for deployment.
For customers, the change should be largely invisible in the near term: Micron is not abandoning DRAM development, only one proposed cell architecture. The immediate battle remains focused on density, bandwidth, power efficiency and manufacturing yields for AI systems. In the longer run, however, Micron’s rejection of 4F² could make vertical or stacked memory the industry’s more important frontier—and turn a once-promising two-dimensional shortcut into a technological dead end.
